A1.1 Computer hardware and operation

The Program Counter (PC) holds the memory address of the next instruction to be fetched. Every fetch begins here.

The address in the PC is copied to the Memory Address Register (MAR). The MAR is the register that interfaces with the address bus.

The address travels along the address bus (one-way, CPU → memory) to locate the correct memory location. The Control Unit issues a READ signal on the control bus.

The instruction stored at that address is sent back to the CPU along the data bus (bidirectional) and placed into the Memory Data Register (MDR).

Finally, the instruction is copied from the MDR into the Instruction Register (IR), ready for decoding. The correct sequence is PC → MAR → address bus → memory → data bus → MDR → IR.

We need to identify the correct ordered path taken by an instruction during the Fetch phase, from memory to the CPU's Instruction Register.

PC → IR → MAR → data bus → MDR is wrong. The IR is not involved before the MAR, and the instruction cannot reach the IR before it has been fetched from memory.

MAR → PC → control bus → memory → IR → MDR is wrong. The PC comes before the MAR, not after it, and the instruction must go to the MDR before the IR, not after.

IR → MAR → data bus → memory → PC → MDR is wrong. The IR should be the final destination in the fetch phase, not the starting point, and the PC does not come after memory.

PC → MAR → address bus → memory → data bus → MDR → IR is the only option that correctly reflects every register and bus in the right order during the Fetch phase.

We need the component that interprets opcodes and signals other components to act — this is the coordination role within the CPU.

The ALU performs arithmetic and logical operations (e.g. ADD, AND, compare). It does not interpret opcodes or issue control signals.

The MDR temporarily holds data transferred between CPU and memory. The ACC stores results of ALU operations. Neither interprets instructions.

The Control Unit (CU) reads the instruction from the IR, splits it into opcode and operand, interprets the opcode, and sends control signals to the ALU, registers, and buses to carry out execution.

The Control Unit (CU) is the coordinator of the entire FDE cycle. It does not process data itself but directs every other component.

We need the CPU component that interprets the opcode portion of an instruction and signals other components to act accordingly.

The ALU executes arithmetic and logic, but it does not interpret opcodes or issue control signals — it only acts when told to by another component.

The MDR is a temporary buffer for data being read from or written to memory. It plays no role in interpreting instructions.

The Accumulator stores the results of ALU calculations. It is passive during the decode phase and does not interpret any instruction.

The Control Unit (CU) is the only component that reads the IR, interprets the opcode, and directs all other parts of the CPU. It is the coordinator of the FDE cycle.